The UVM environment is written for APB master and the DUT slave is verified according to the functionaluty of APB.

To design and verify the 4x4 router by developing environment in UVM.

The UVM compliant APB master UVC supports APB protocol functionality w.r.t master. This UVC verifies the APB slave functionality. It consists of a complete set of verification capabilities like sequencer, checker and coverage metrics.

To design and verify the Memory by developing environment in System Verilog.

To Design and Verify the configurable arbiter.