Design Verification Engineer | Online Jobs | Optimhire

Design Verification Engineer

Job Description:


  • UVM, SV, C/C++ based verification.
  • Strong knowledge of SV/ UVM based debugging.
  • Experience in constraint randomization based verification.
  • Strong knowledge of UVM assertion based verification."
  • ARM CPU based verification.
  • Should have develop verification bench architecture, Test plan, coverage & assertion plans.
  • Gate Level simulation & debugging.
  • Should have develop verification bench architecture, Test plan, coverage & assertion plans.
  • Candidates having 3+ years to 15 years of Industry Experience is counted


Job Type

Payroll


Positions

Full-Stack Developers


Must have Skills

  • C++ - 3 Years

    Advanced

  • Universal Verification Methodology - UVM - 3 Years

    Advanced

11 - 107 K/Year USD (Annual salary)

Longterm (Duration)

Onsite Bengaluru, Karnataka, India


Shimoni P

India