Design Verification Engineer
Job Description:
- UVM, SV, C/C++ based verification.
- Strong knowledge of SV/ UVM based debugging.
- Experience in constraint randomization based verification.
- Strong knowledge of UVM assertion based verification."
- ARM CPU based verification.
- Should have develop verification bench architecture, Test plan, coverage & assertion plans.
- Gate Level simulation & debugging.
- Should have develop verification bench architecture, Test plan, coverage & assertion plans.
- Candidates having 3+ years to 15 years of Industry Experience is counted
Job Type
Payroll
Positions
Full-Stack Developers
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11 - 107 K/Year USD (Annual salary)
Longterm (Duration)
Onsite Bengaluru, Karnataka, India
Shimoni P