Narayana C.

Narayana C.

VLSI, Electronic Design Automation and Embedded Systems Engineer

Hyderabad , India

Experience: 25 Years

Narayana

Hyderabad , India

VLSI, Electronic Design Automation and Embedded Systems Engineer

18520.5 USD / Year

  • Immediate: Available

25 Years

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About Me

General Manager with over 25 years of experience in Embedded System Products, EDA (co-verificationtools), IP Design/Verification, Embedded software and System Design (Telecom) I am in a sabbatical break from 2019 Feb, focussing on learing new prog...

1. VLSI- Frontend - Hardware Modeling in VHDL & Verilog. Domain - Telecom (SDH, ATM)

2. EDA - HW-SW Co-verification Tool - Instruction Simulator, Bus Functional Models in C, C++

3. Linux based Embedded Systems

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Portfolio Projects

Head of Embedded HW and SW Groups

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1. Product Architecture 2. Product Certification (EMV L1, EMV L2, RD Certifications) 3. Interface to Customer, Production and Sales Groups 4. Software Development Kit for System Integrators.

Description

1. Heading a Team of Embedded HW and SW Teams (totally 60 engineers). My role was in Product Architecture, Product Development and Maintenance. This product is used by both inhouse and external system integrators. Interfaced with inhouse and external groups. Involved in Product Certification. Individually developed a Java ME wrapper for the product - porting JDK, JNIwrapper and sample Java diagnostic application.

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Seamless- coverification tool development, Instruction Set Simulators, BFMs

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I joined as a Founding Member of seamless India and executed the initial project successfully. Subsequently for more than a decade, I managed the team which grew up to the size of 22.

Description

Initially as a starting member of the team involved in development of Bus Functional Model and ISS in C. Later as a Manager for a team of 22 for both Seamless and couple of Embedded Groups. Domain knowledge in ARM, MIPS, PPC etc.

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Contribute

Worked for AMD at Milpitas for six months.My contribution was in cell characterization (functional and timing) for one of their Ethernet chip.

Description

Worked for AMD at Milpitas for six months. My contribution was in cell characterization (functional
and timing) for one of their Ethernet chip.
Testing of a Formal Verification tool.
Running Spice decks for power characterization works.

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I worked in both development and verification of ATM Framers and ATM Switch IP.

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I worked in both development and verification of ATM Framers and ATM Switch IP.

Description

Verification of ATM Switch IP cores. I developed a behavioral representation of ATM Switch IP at a
higher abstraction. This was used as a golden model for testing the RTL. I implemented various
testbench elements like Pseudo Random ATM Cell generators, Scoreboards etc.
Development of Built in Self Test for ATM E3/DS3 Framers. The piece of RTL went as part of IP and
later for a customer chip.
Development of E3 Framer for ATM Core Cell. This was part of an E3/DS3 framer chip.

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Telecom Transmission systems (PDH & SDH systems)

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Development of Fiber optic Telecommunication System.My contribution was in development of Manchester encoder and decoder using Altera EPLD and clock extraction circuitry Board level testing of SONET

Description

Development of Fiber optic Telecommunication System. My contribution was in development of
Manchester encoder and decoder using Altera EPLD and clock extraction circuitry
Board level testing of SONET/PDH transmission systems.

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